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PDF iT4005D Data sheet ( Hoja de datos )
| Número de pieza | iT4005D | |
| Descripción | 12-Gb/s GaAs MMIC D flip-flop | |
| Fabricantes | Iterra | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de iT4005D (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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iT4005D
12.5 Gb/s GaAs MMIC D Flip-Flop
(Advanced Information)
Description
www.DataSheet4U.com
Features
The iT4005D is a high-speed D-type flip flop fabricated using 1-μm HBT GaAs technology. Its
high output voltage, excellent rise and fall time and the high eye diagram quality at all clock
frequencies makes the iT4005D suitable for very high speed and complex digital applications
such as decision circuits, waveform shaping, register implementation, and timing adjustment.
The device consists of a master-slave latch designed using an ECL topology guarantee high-
speed operation. The data and clock inputs and data outputs are DC coupled. At the data input
port, the iT4005D tolerates a wide range of operating conditions, and the internal 50-ohm
resistors avoid the need for external terminations for impedance matching. The iT4005D uses
SCFL I/O levels and allows either single-ended or differential data input and output. For the
clock, a single-ended, DC-coupled input with an internal 50-ohm resistor followed by a DC block
is provided. An amplitude of 700 mV peak-to-peak for the clock is recommended, although
depending on the operating frequency, a lower amplitude may be usable. An on-chip output
buffer provides an excellent eye diagram at a 12.5 GHz clock frequency.
2-13 GHz clock frequency range
900 mVpp single ended output dynamic
Output rise time (20%-80%): 25 ps
Output fall time (20%-80%): 24 ps
DC coupled clock input
DC coupled data input
50 ohm matched DC-coupled data output
Differential or single-ended inputs
Low power consumption:
1 W at -5.2 V (VQH = 0.0 V, VQL = -0.9 V)
0.7 W at -4.5 V (VQH = 0.0 V, VQL = -0.6 V)
0.5 W at -4.0 V (VQH = 0.0 V, VQL = -0.4 V)
Device
Diagram
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4047 Rev 0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
1 page  
Eye Diagram
Performance
(cont.)
www.DataSheet4U.com
Recommended
Operational
Setup
Bias Conditions
Connect inputs
Apply -5.0 V at Vee
Apply RF signals to
the inputs
Tune Vindc for
optimal eye diagram
in case of single-
ended input.
iT4005D
12.5 Gb/s GaAs MMIC D Flip-Flop
(Advanced Information)
Q
Output at 12.5 Gb/s. Power supply = -4 V
Q\
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4047 Rev 0
5
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet iT4005D.PDF ] | |
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