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PDF SY100E131 Data sheet ( Hoja de datos )
| Número de pieza | SY100E131 | |
| Descripción | 4-BIT D FLIP-FLOP | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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4-BIT D
FLIP-FLOP
SY10E131
SY100E131
FEATURES
s 1100MHz min. toggle frequency
s Extended 100E VEE range of –4.2V to –5.5V
s Differential output
s Individual and common clocks
s Indivldual asynchronous reset
s Paired asynchronous sets
s Fully compatible with Industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E131
s Available in 28-pin PLCC package
PIN CONFIGURATION
CE3
D3
S12
VEE
CC
S03
D0
25 24 23 22 21 20 19
26 18
27 17
28
PLCC
16
1
TOP VIEW
15
J28-1
2 14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
Q0
Q0
DESCRIPTION
The SY10/100E131 are high-speed quad master slave
D-type flip-flops with differential outputs designed for use
in new, high-performance ECL systems. The flip-flops may
be individually clocked by holding CC (Common Clock) at
a logic LOW and then using the four individual CE (Clock
Enable CE0–CE3) inputs to accomplish such clocking.
Alternatively, all four flip-flops can be clocked in common
by holding the CE inputs LOW and then using CC to clock
the data. In the common clock mode, the CE input acts as
a control that passes the CC signal to the flip-flop. Data is
clocked into the flip-flop on the rising edge of the output of
the logical OR operation between CE and CC (data enters
the master when both CC and CE are LOW and data
transfers to the slave when either CE or CC, or both, go
HIGH).
Asynchronous set and reset controls are provided. The
reset controls are individual and the set controls are
pairwise.
PIN NAMES
Pin
D0-D3
CE0-CE3
R0-R3
CC
S03, S12
Q0-Q3
Q0-Q3
VCCO
Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
VCC to Output
Rev.: E Amendment: /0
1 Issue Date: November, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E131.PDF ] | |
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