SY100E431 반도체 회로 부품 판매점
3-BIT DIFFERENTIAL FLIP-FLOP
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 Micrel Semiconductor |
3-BIT DIFFERENTIAL
FLIP-FLOP
SY10E431
SY100E431
FEATURES
s Differential D, clock and Q
s Extended 100E VEE range of –4.2V to –5.5V
s VBB output for single-ended use
s 1100MHz min. toggle frequency
s Edge-triggered asynchronous set and reset
s Fully compatible with Motorola MC10E/100E431
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100E431 are 3-bit flip-flops with differential
clock, data input and data output.
The asynchronous Set and Reset controls are edge-
triggered rather than level controlled. This allows the user
to rapidly set or reset the flip-flop and then continue
clocking at the next clock edge without the necessity of
de-asserting the set/reset signal (as would be the case
with a level controlled set/reset).
The E431 is also designed with larger internal swings,
an approach intended to minimize the time spent crossing
the threshold region and thus reduces the metastability
susceptibility window.
S0
D0
D0
CLK0
CLK0
R0
S1
D1
D1
CLK1
CLK1
R1
S2
D2
D2
CLK2
CLK2
R2
S
DQ
Q
R
Q0
Q0
S
DQ
Q
R
Q1
Q1
S
DQ
Q
R
Q2
Q2
PIN CONFIGURATION
CLK1
CLK1
R1
VEE
S1
D1
D1
25 24 23 22 21 20 19
26 18
27 17
28 TOP VIEW 16
1
PLCC
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
Q0
Q0
PIN NAMES
VBB
TRUTH TABLE(1)
Dn CLKn
LZ
HZ
XL
XL
NOTE:
1. Z = LOW-to-HIGH transition.
Rn
L
L
Z
L
Sn
L
L
L
Z
Pin Function
D[0:2], D[0:2]
Differential Data Inputs
CLK[0:2], CLK[0:2] Differential Clock Inputs
Qn S[0:2]
L R[0:2]
H VBB
L Q[0:2], Q[0:2]
H VCCO
Edge Triggered Set Inputs
Edge Triggered Reset Inputs
VBB Reference Output
Differential Data Outputs
VCC to Output
Rev.: C Amendment: /1
1 Issue Date: February, 1998
Micrel
SY10E431
SY100E431
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
Symbol
Parameter
TA = 0°C
TA = +25°C
TA = +85°C
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VBB Output Reference Voltage
V
10E –1.38 — –1.27 –1.35 — –1.25 –1.31 — –1.19
100E –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26
IIH Input HIGH Current
— — 150 — — 150 — — 150 µA
IEE Power Supply Current
mA
10E — 110 132 — 110 132 — 110 132
100E — 110 132 — 110 132 — 127 152
VCMR Common Mode Range
–1.5 — 0 –1.5 — 0 –1.5 — 0 V
Condition
—
—
—
1
NOTES:
1. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the VCMR range
and the input swing is greater than VPP (min.) and <1V.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
Min. Typ. Max.
TA = +25°C
Min. Typ. Max.
TA = +85°C
Min. Typ. Max.
Unit
Condition
fMAX
Max. Toggle Frequency
1100 1400 — 1100 1400 — 1100 1400 — MHz
—
tPLH Propagation Delay to Output
ps
tPHL CLK (Diff)
450 600 750 450 600 750 450 600 750
CLK (SE)
400 600 800 400 600 800 400 600 800
R 550 725 925 550 725 925 550 725 925
S 550 725 925 550 725 925 550 725 925
—
tS Set-up Time
D
R
S
200
1000
1000
0
700
700
— 200 0
— 1000 700
— 1000 700
— 200 0
— 1000 700
— 1000 700
—
—
—
ps
1
1
tH Hold Time, D
200 0
— 200 0
— 200 0
— ps
—
tPW
tskew
Minimum Pulse Width, CLK 400 — — 400 — — 400 — — ps
Within-Device Skew
— 50 — — 50 — — 50 — ps
—
2
VPP (AC) Minimum Input Swing
150 — — 150 — — 150 — — mV
3
tr Rise/Fall Time
tf 20% to 80%
275 450 650 275 450 650 275 450 650 ps
—
NOTES:
1. These set-up times define the minimum time the CLK or SET/RESET input
must wait after the assertion of the RESET/SET input to assure the proper
operation of the flip-flop.
2. Within-device skew is defined as identical transitions on similar paths
through a device.
3. Minimum input swing for which AC parameters are guaranteed.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY10E431JC
J28-1
Commercial
SY10E431JCTR
J28-1
Commercial
SY100E431JC
J28-1
Commercial
SY100E431JCTR
J28-1
Commercial
2
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제조업체: Micrel Semiconductor
( micrel )
SY100E431 flip-flop
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