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74HC374 반도체 회로 부품 판매점

Octal D-type flip-flop positive edge-trigger 3-state



Philips 로고
Philips
74HC374 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT374
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990


74HC374 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
74HC/HCT374
FEATURES
3-state non-inverting outputs for bus oriented
applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT374 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT374 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The “374” is functionally identical to the “534”, but has
non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC
15
77
3.5
17
HCT
13
48
3.5
17
UNIT
ns
MHz
pF
pF
December 1990
2




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74HC374 flip-flop

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