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74F821SPC 반도체 회로 부품 판매점

10-Bit D-Type Flip-Flop



Fairchild 로고
Fairchild
74F821SPC 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F821
10-Bit D-Type Flip-Flop
General Description
The 74F821 is a 10-bit D-type flip-flop with 3-STATE true
outputs arranged in a broadside pinout.
Features
s 3-STATE Outputs
Ordering Code:
Order Number Package Number
Package Description
74F821SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F821SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009595
www.fairchildsemi.com


74F821SPC 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
D0–D9
OE
CP
O0–O9
Description
Data Inputs
Output Enable
3-STATE Input
Clock Input
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
1.0/1.0
20 µA/0.6 mA
150/40 (33.3) 3.0 mA/24 mA (20 mA)
Functional Description
The 74F821 consists of ten D-type edge-triggered flip-
flops. This device has 3-STATE true outputs for bus sys-
tems organized in a broadside pinning. The buffered Clock
(CP) and buffered Output Enable (OE) are common to all
flip-flops. The flip-flops will store the state of their individual
D inputs that meet the setup and hold times requirements
on the LOW-to-HIGH CP transition. With the OE LOW the
content of the flip-flops are available at the outputs. When
the OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the state of
the flip-flops.
Function Table
Inputs
OE CP
HH
HL
H
H
L
L
LH
LL
D
X
X
L
H
L
H
X
X
Internal Output
QO
Function
NC Z Hold
NC Z Hold
H Z Load
L Z Load
H L Data Available
L H Data Available
NC NC No Change in Data
NC NC No Change in Data
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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