파트넘버.co.kr 74F74 데이터시트 PDF


74F74 반도체 회로 부품 판매점

Dual D-Type Positive Edge-Triggered Flip-Flop



National 로고
National
74F74 데이터시트, 핀배열, 회로
December 1994
54F 74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The ’F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q Q) outputs Information at the
input is transferred to the outputs on the positive edge of
the clock pulse Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the transition
time of the positive-going pulse After the Clock Pulse input
threshold voltage has been passed the Data input is locked
out and information present will not be transferred to the
outputs until the next rising edge of the Clock Pulse input
Asynchronous Inputs
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Features
Y Guaranteed 4000V minimum ESD protection
Commercial
74F74PC
74F74SC (Note 1)
74F74SJ (Note 1)
Military
54F74DM (Note 2)
54F74FM (Note 2)
54F74LM (Note 2)
Package
Number
N14A
J14A
M14A
M14D
W14B
E20A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use Suffix e SCX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9469–3
TL F 9469 – 4
TL F 9469 – 6
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9469
RRD-B30M75 Printed in U S A


74F74 데이터시트, 핀배열, 회로
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9469–1
Unit Loading Fan Out
Pin Names
D1 D2
CP1 CP2
CD1 CD2
SD1 SD2
Q1 Q1 Q2 Q2
Description
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 30
10 30
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 8 mA
20 mA b1 8 mA
b1 mA 20 mA
TL F 9469 – 2
Truth Table
Inputs
Outputs
SD CD CP D Q
Q
L H X XH L
HL
X XL H
L L X XH H
H H Lh H L
H HLl L H
HH
L X Q0 Q0
H (h) e HIGH Voltage Level
L (l) e LOW Voltage Level
X e Immaterial
Q0 e Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one
setup time prior to the LOW-to-HIGH clock transition
Logic Diagram
TL F 9469 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2




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74F74 flip-flop

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