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74F564SJ 반도체 회로 부품 판매점

Octal D-Type Flip-Flop with 3-STATE Outputs



Fairchild 로고
Fairchild
74F564SJ 데이터시트, 핀배열, 회로
www.DataSheet4U.com
April 1983
Revised October 2000
74F564
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F564 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Out-
put Enable (OE). The information presented to the D inputs
is sorted in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
This device is functionally identical to the 74F574, but has
inverted outputs.
Features
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to 74F574
s 3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number Package Number
Package Description
74F564SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F564PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS009563
www.fairchildsemi.com


74F564SJ 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
D0D7
CP
OE
O0O7
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
1.0/1.0
20 µA/0.6 mA
1.0/1.0
20 µA/0.6 mA
1.0/1.0
20 µA/0.6 mA
150/40 (33.3) 3 mA/24 mA (20 mA)
Functional Description
The 74F564 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the
flip-flops.
Function Table
Inputs
Internal Outputs
OE CP D
Q
O
Function
H H L NC
Z Hold
HHH
H L
H H
L L
L H
NC
H
L
H
L
Z Hold
Z Load
Z Load
H Data Available
L Data Available
L H L NC
NC No Change in Data
L H H NC
NC No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild