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74F534 반도체 회로 부품 판매점

Octal D-Type Flip-Flop with 3-STATE Outputs



Fairchild 로고
Fairchild
74F534 데이터시트, 핀배열, 회로
www.DataSheet4U.com
April 1988
Revised October 2000
74F534
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F534 is a high speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The 74F534 is the same as the 74F374 except that
the outputs are inverted.
Features
s Edge-triggered D-type inputs
s Buffered positive edge-triggered clock
s 3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number Package Number
Package Description
74F534SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F534SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F534PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS009549
www.fairchildsemi.com


74F534 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
D0D7
CP
OE
O0O7
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
Complementary 3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40(33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
3 mA/24 mA (20 mA)
Function Table
Inputs
Output
CP OE D
LH
LL
L LX
X HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Clock Transition
O0 = Value stored from previous clock cycle
O
L
H
O0
Z
Functional Description
The 74F534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74F534 flip-flop

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