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74F533 반도체 회로 부품 판매점

Latch/flip-flop



Philips 로고
Philips
74F533 데이터시트, 핀배열, 회로
www.DataSheet4U.com
INTEGRATED CIRCUITS
74F533*,74F534
Latch/flip-flop
* Discontinued part. Please see the Discontinued Product List.
Product specification
Supersedes data of 1989 May 11
IC15 Data Handbook
Philips
Semiconductors
1999 Jan 08


74F533 데이터시트, 핀배열, 회로
Philips Semiconductors
Latch/flip-flop
Product specification
74F533,* 74F534
74F533 Octal Transparent Latch, Inverting (3-State)
74F534 Octal D Flip-Flop, Inverting (3-State)
FEATURES
8-bit positive edge-triggered register – 74F534
3-State inverting output buffers
Common 3-State Output register
Independent register and 3-State buffer operation
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
DESCRIPTION
The 74F533 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
The 74F534 is an 8-bit edge-triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the Clock (CP) and Output Enable (OE) control
gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
TYPE
TYPICAL
PROPAGATION DELAY
74F533
5.5ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
41mA
TYPE
74F534
TYPICAL fMAX
165MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
51mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
20-Pin Plastic DIP
N74F534N
20-Pin Plastic SOL
N74F534D
PKG DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0 - D7
E (74F533)
OE
CP (74F534)
Q0 - Q7
Data inputs
Enable input (active High)
Output Enable input (active Low)
Clock Pulse input (active rising edge)
Data outputs
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
* Discontinued part. Please see the Discontinued Products List.
1999 Jan 08
2
853-0374 20616




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