74F273 반도체 회로 부품 판매점

Octal D-Type Flip-Flop



Fairchild 로고
Fairchild
74F273 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Ideal buffer for MOS microprocessor or memory
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous Master Reset
s See 74F377 for clock enable version
s See 74F373 for transparent latch version
s See 74F374 for 3-STATE version
Ordering Code:
Order Number Package Number
Package Description
74F273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009511
www.fairchildsemi.com

74F273 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
1 mA/20 mA
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load “1”
Load “0”
Inputs
Output
MR CP Dn Qn
LXXL
H h H
H l
L
H = HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
= LOW-to-HIGH clock transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74F273 flip-flop

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