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Fairchild Semiconductor |
www.DataSheet4U.com
January 2000
Revised June 2005
74VCXH16374
Low Voltage 16-Bit D-Type Flip-Flops with Bushold
General Description
The VCXH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The VCXH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74VCXH16374 is designed for low voltage (1.4V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74VCXH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
3.0 ns max for 3.0V to 3.6V VCC
s Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number
Package Descriptions
74VCXH16374GX
(Note 1)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74VCXH16374MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500228
www.fairchildsemi.com
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
OEn
CPn
I0–I15
O0–O15
NC
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G O12 O11
H O14 O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE2
4
CP1
NC
VCC
GND
GND
GND
VCC
NC
CP2
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
Outputs
CP1
OE1
L
I0–I7
H
O0–O7
H
L L L
L L X O0
XHXZ
Inputs
Outputs
CP2
OE2
L
I8–I15
H
O8–O15
H
L L L
L L X O0
XHXZ
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, control inputs may not float)
Z High Impedance
O0 Previous O0 before HIGH-to-LOW of CP
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