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74LVX574 반도체 회로 부품 판매점

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LVX574 데이터시트, 핀배열, 회로
June 1993
Revised March 1999
74LVX574
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVX574 is a high-speed octal D-type flip-flop which is
controlled by an edge-triggered clock input (CP) and a buff-
ered common Output Enable (OE) input. When the OE
input is HIGH, the eight outputs are in a high impedance
state. The LVX574 is functionally identical to the LVX374
but with inputs and outputs on opposite sides of the pack-
age. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX574M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500050.prf
www.fairchildsemi.com


74LVX574 데이터시트, 핀배열, 회로
Functional Description
The LVX574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Truth Table
Inputs
Dn CP
H
L
XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
OE
L
L
H
Outputs
On
H
L
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVX574 flip-flop

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