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Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LVTH574MSA 데이터시트, 핀배열, 회로
March 1999
Revised March 1999
74LVT574 • 74LVTH574
Low Voltage Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT574 and LVTH574 are high-speed, low-power
octal D-type flip-flop featuring separate D-type inputs for
each flip-flop and 3-STATE outputs for bus-oriented appli-
cations. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The LVTH574 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT574 and LVTH574
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V
VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH574), also
available without bushold feature (74LVT574).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 574
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, .300” Wide
74LVT574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVT574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVT574MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, .300” Wide
74LVTH574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVTH574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH574MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012451.prf
www.fairchildsemi.com


74LVTH574MSA 데이터시트, 핀배열, 회로
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Truth Table
Functional Description
The LVT574 and LVTH574 consist of eight edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The buffered clock and buffered Output Enable
are common to all flip-flops. The eight flip-flops will store
the state of their individual D-type inputs that meet the
setup and hold time requirements on the LOW-to-HIGH
Logic Diagram
Inputs
Dn CP OE
HL
L L
XLL
XXH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Oo = Previous Oo before HIGH to LOW of CP
Outputs
On
H
L
Oo
Z
Clock (CP) transition. With the Output Enable (OE) LOW,
the contents of the eight flip-flops are available at the out-
puts. When the OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip-flops.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor