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PDF 74LVTH162374MTX Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH162374MTX | |
| Descripción | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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June 2000
Revised August 2001
74LVTH162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25Ω Series Resistors in the Outputs
General Description
The LVTH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The LVTH162374 is designed with equivalent 25Ω series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH162374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Power Down high impedance provides
glitch-free bus loading
s Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Functionally compatible with the 74 series 16374
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
Package
Number
Package Description
74LVTH162374GX
(Note 1)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LVTH162374MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
74LVTH162374MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LVTH162374MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
© 2001 Fairchild Semiconductor Corporation DS500355
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICCZ+
Power Supply Current
VCC
T A = −40°C to +85°C
Units
(V) Min Max
3.6 0.19 mA
∆ICC
Increase in Power Supply Current
(Note 6)
3.6
0.2 mA
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 7)
Symbol
Parameter
VCC TA = 25°C
Units
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
V
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
Conditions
CL = 50 pF, RL = 500Ω
(Note 8)
(Note 8)
AC Electrical Characteristics
TA = −40°C to +85°C, CL = 50 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
fMAX
Maximum Clock Frequency
160 150 MHz
tPHL Propagation Delay
tPLH
CP to On
2.0 5.1 2.0 5.3
ns
1.6 5.3 1.6 6.2
tPZL
tPZH
Output Enable Time
1.8 5.0 1.8 6.0
ns
1.2 5.6 1.2 6.9
tPLZ
tPHZ
Output Disable Time
1.9 5.0 1.9 5.1
ns
2.0 5.4 2.0 5.7
tS Setup Time
1.8 2.0
ns
tH Hold Time
0.8 0.1
ns
tW Pulse Width
3.0 3.0
ns
tOSHL
tOSLH
Output to Output Skew (Note 9)
1.0 1.0
ns
1.0 1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = OPEN, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74LVTH162374MTX.PDF ] | |
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