|
NXP Semiconductors |
INTEGRATED CIRCUITS
74LVT273
3.3V Octal D flip-flop
Product specification
Supersedes data of 1994 May 11
IC23 Data Handbook
Philips
Semiconductors
1998 Feb 19
Philips Semiconductors
3.3V Octal D flip-flop
Product specification
74LVT273
FEATURES
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous Master Reset
• Output capability: +64mA/–32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Power-up reset
• Live insertion/extraction permitted
• No bus current loading when output is tied to 5V bus
• Latchup protection exceeds 500 mA per JEDEC Std 17
• ESD protection exceeds 2000V per Mil Std 883 Method 3015 and
200V per Machine Model.
DESCRIPTION
The LVT273 is a high-performance BiCMOS product designed for
VCC operation at 3.3V.
This device has eight edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common buffered Clock (CP) and
Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
All outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common elements.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL
CP to Qn
CIN Input capacitance
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 3.3V
VI = 0V or 3.0V
TYPICAL
3.5
3.5
4
UNIT
ns
pF
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT273 D
74LVT273 DB
74LVT273 PW
NORTH AMERICA
74LVT273 D
74LVT273 DB
74LVT273PW DH
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
LOGIC SYMBOL
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SV00017
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11 CP
1 MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SV00018
1998 Feb 19
2 853-1740 18985
|