74LVQ374SC 반도체 회로 부품 판매점
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
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 Fairchild Semiconductor |
May 1998
74LVQ374
Low Voltage Octal D-Type Flip-Flop with 3-STATE
Outputs
General Description
The LVQ374 is a high-speed, low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
n Buffered positive edge-triggered clock
n 3-STATE outputs drive bus lines or buffer memory
address registers
Ordering Code:
Order Number
74LVQ374SC
74LVQ374SJ
74LVQ374QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SOIC JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
IEEE/IEC
DS011360-1
DS011360-3
DS011360-2
© 1998 Fairchild Semiconductor Corporation DS011360
www.fairchildsemi.com
Pin Descriptions
Pin Names
D0– D7
CP
OE
O0– O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Functional Description
The LVQ374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The buff-
ered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D-type inputs that meet the setup and hold time re-
Logic Diagram
Truth Table
Inputs
Dn CP
HN
LN
XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
OE
L
L
H
Outputs
On
H
L
Z
quirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight
flip-flops are available at the outputs. When the OE is HIGH,
the outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
DS011360-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVQ374SC flip-flop
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관련 데이터시트
74LVQ374SC
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor
74LVQ374SJ
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor