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Fairchild Semiconductor |
April 1998
74LVQ273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVQ273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ273SC
74LVQ273SJ
74LVQ273QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
20-Lead Shrink Molded Small Outline Package, SOIC EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011358-1
IEEE/IEC
DS011358-2
DS011358-3
Pin Descriptions
Pin Names
D0– D7
MR
CP
Q0– Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1998 Fairchild Semiconductor Corporation DS011358
www.fairchildsemi.com
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-up Source or
Sink Current
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
±400 mA
−65˚C to +150˚C
±300 mA
DC Electrical Characteristics
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
2.0V to 3.6V
0V to VCC
0V to VCC
−40˚C to +85˚C
VIN from 0.8V to 2.0V
VCC @ 3.0V
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for ac-
tual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
VOL Maximum Low Level
Output Voltage
IIN
IOLD
IOHD
ICC
VOLP
VOLV
VIHD
VILD
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
VCC
TA = +25˚C
TA = −40˚C to +85˚C Units
Conditions
(V) Typ
Guaranteed Limits
3.0 1.5
2.0
2.0
V VOUT = 0.1V
or VCC − 0.1V
3.0 1.5
0.8
0.8
V VOUT = 0.1V
3.0 2.99
3.0
3.0 0.002
3.0
3.6
2.9
2.58
0.1
0.36
±0.1
2.9
2.48
0.1
0.44
±1.0
or VCC − 0.1V
V IOUT = −50 µA
V VIN = VIL or VIH (Note 3)
IOH = −12 mA
V IOUT = 50 µA
V VIN = VIL or VIH (Note 3)
IOL = 12 mA
µA VI = VCC, GND
3.6 36 mA VOLD = 0.8V Max (Note 5)
3.6 −25 mA VOHD = 2.0V Min (Note 5)
3.6
4.0
40.0
µA VIN = VCC or GND
3.3 0.4
0.8
V (Notes 6, 7)
3.3 −0.3
−0.8
V (Notes 6, 7)
3.3 1.7
2.0
V (Notes 6, 8)
3.3 1.6
0.8
V (Notes 6, 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
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