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74LVQ174 반도체 회로 부품 판매점

Low Voltage Hex D-Type Flip-Flop with Master Reset



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LVQ174 데이터시트, 핀배열, 회로
May 1998
74LVQ174
Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
The LVQ174 is a high-speed hex D-type flip-flop. The device
is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage dur-
ing the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75
Ordering Code:
Order Number
74LVQ174SC
74LVQ174SJ
Package Number
M16A
M16D
Package Description
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC JEDEC and EIAJ
IEEE/IEC
DS011353-1
DS011353-2
DS011353-3
Pin Descriptions
Pin Names
D0– D5
CP
MR
Q0– Q5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
© 1998 Fairchild Semiconductor Corporation DS011353
www.fairchildsemi.com


74LVQ174 데이터시트, 핀배열, 회로
Functional Description
The LVQ174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Mas-
ter Reset (MR) are common to all flip-flops. Each D input’s
state is transferred to the corresponding flip-flop’s output fol-
lowing the LOW-to-HIGH Clock (CP) transition. A LOW input
to the Master Reset (MR) will force all outputs LOW indepen-
dent of Clock or Data inputs. The LVQ174 is useful for appli-
cations where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Logic Diagram
Truth Table
Inputs
MR CP
LX
HN
HN
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
D
X
H
L
X
Output
Q
L
H
L
Q
DS011353-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74LVQ174 flip-flop

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