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INTEGRATED CIRCUITS
DATA SHEET
74LVCH32374A
32-bit edge-triggered D-type
flip-flop with 5 V tolerant
inputs/outputs; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Nov 24
Philips Semiconductors
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
Product specification
74LVCH32374A
FEATURES
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTE™ flow-trough standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs
• Typical output ground bounce voltage:
VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
• Typical output undershoot voltage:
VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C
• Power off disables outputs, permitting live insertion
• Packaged in plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVCH32374A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 or 5 V environment.
The 74LVCH32374A is a 32-bit edge-triggered flip-flop
featuring separate D-type inputs for each flip-flop and
3-state outputs for bus oriented applications. The
74LVCH32374A consists of 4 sections of eight
edge-triggered flip-flops. A clock (nCP) input and an
output enable input (nOE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs
that meet the set-up and hold time requirements on the
LOW-to-HIGH nCP transition.
When input nOE is LOW, the contents of the flip-flops are
available at the outputs. When input nOE is HIGH, the
outputs go to the high-impedance OFF-state. Operation of
the nOE input does not affect the state of the flip-flops.
The 74LVCH32374A bus hold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
tPHL/tPLH
fmax
CI
CPD
propagation delay nCP to nQn
maximum clock frequency
input capacitance
power dissipation capacitance per
buffer
CONDITIONS
CL = 50 pF; VCC = 3.3 V
VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
3.8
150
5.0
30
UNIT
ns
MHz
pF
pF
1999 Nov 24
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