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74LVC821A 반도체 회로 부품 판매점

10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State



NXP Semiconductors 로고
NXP Semiconductors
74LVC821A 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LVC821A
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger
(3-State)
Product specification
1998 Sep 25
Philips
Semiconductors


74LVC821A 데이터시트, 핀배열, 회로
Philips Semiconductors
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
Product specification
74LVC821A
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
10-bit positive edge-triggered register
Independent register and 3-State buffer operation
Flow-through pin-out architecture
DESCRIPTION
The 74LVC821A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops. The ten flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the contents
of the ten flip-flops is available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
Propagation delay
CP to Qn
Maximum clock frequency
CL = 50 pF;
VCC = 3.3 V
CI Input capacitance
CPD
Power dissipation capacitance per
flip-flop
Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
TYPICAL
5.4
150
5.0
26
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDERING CODE
74LVC821A D
74LVC821A DB
74LVC821A PW
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
1998 Sep 25
2 853-1970 20088




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