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74LVC74APW 반도체 회로 부품 판매점

Dual D-type flip-flop with set and reset; positive-edge trigger



NXP Semiconductors 로고
NXP Semiconductors
74LVC74APW 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
IC24 Data Handbook
1998 Jun 17
Philips
Semiconductors


74LVC74APW 데이터시트, 핀배열, 회로
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product Specification
74LVC74A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 W transmission lines @ 85°C
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.
The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 50 pF;
VCC = 3.3 V
fmax Maximum clock frequency
CI Input capacitance
CPD Power dissipation capacitance per flip-flop Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) +ȍ (VO2/RL) × duty factor LOW, where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
3.6
3.5
3.5
250
5.0
30
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74A PW
NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74APW DH
UNIT
ns
MHz
pF
pF
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1RD 1
1D 2
1CP 3
1SD 4
1Q 5
1Q 6
GND 7
14 VCC
13 2RD
12 2D
11 2CP
10 2SD
9 2Q
8 2Q
SV00491
4S
3 C1
2 1D
1R
10 S
11 C2
12 2D
13 R
5
6
9
8
SV00332
1998 Jun 17
2 853-2070 19589




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74LVC74APW flip-flop

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