파트넘버.co.kr 74LVC1G80GW 데이터시트 PDF


74LVC1G80GW 반도체 회로 부품 판매점

Single D-type flip-flop; positive-edge trigger



Panasonic Semiconductor 로고
Panasonic Semiconductor
74LVC1G80GW 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G80
Single D-type flip-flop;
positive-edge trigger
Product specification
Supersedes data of 2004 Jun 29
2004 Sep 10


74LVC1G80GW 데이터시트, 핀배열, 회로
Philips Semiconductors
Single D-type flip-flop; positive-edge trigger
Product specification
74LVC1G80
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 °C to +85 °C and
40 °C to +125 °C.
DESCRIPTION
The 74LVC1G80 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device in a mixed
3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G80 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
pin on the LOW-to-HIGH transition of the clock pulse.
The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay CP to Q
fmax maximum frequency
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.4 ns
2.3 ns
2.5 ns
2.4 ns
1.8 ns
350 MHz
5.0 pF
17 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2004 Sep 10
2




PDF 파일 내의 페이지 : 총 18 페이지

제조업체: Panasonic Semiconductor

( panasonic )

74LVC1G80GW flip-flop

데이터시트 다운로드
:

[ 74LVC1G80GW.PDF ]

[ 74LVC1G80GW 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


74LVC1G80GM

Single D-type flip-flop; positive-edge trigger - Panasonic Semiconductor



74LVC1G80GV

Single D-type flip-flop; positive-edge trigger - Panasonic Semiconductor



74LVC1G80GW

Single D-type flip-flop; positive-edge trigger - Panasonic Semiconductor