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Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LCX16821MTD 데이터시트, 핀배열, 회로
January 1996
Revised April 1999
74LCX16821
Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant
Inputs and Outputs
General Description
The LCX16821 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is designed for low voltage (2.5V
or 3.3V) VCC applications with capability of interfacing to a
5V signal environment.
The LCX16821 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16821MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16821MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
CLKn
D0–D19
O0–O19
Description
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS012634.prf
www.fairchildsemi.com


74LCX16821MTD 데이터시트, 핀배열, 회로
Connection Diagram
Truth Tables
Functional Description
The LCX16821 contains twenty D-type flip-flops with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. The twenty flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
Logic Diagram
CLK1
X


L or H
Inputs
OE1
H
L
L
L
D0–D9
X
L
H
X
Outputs
O0–O9
Z
L
H
O0
CLK2
X


L or H
Inputs
OE2
H
L
L
L
D10–D19
X
L
H
X
Outputs
O10–O19
Z
L
H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before LOW-to-HIGH transition of Clock
= LOW-to-HIGH transition
ments on the LOW-to-HIGH Clock (CLK) transition. The 3-
STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the flip-flops.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs - Fairchild Semiconductor