|
Fairchild Semiconductor |
February 2001
Revised August 2001
74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26Ω Series Resistors
General Description
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The LCX162374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment. The 26Ω series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs
I 2.3V–3.6V VCC specifications provided
I Equivalent 26Ω series resistor on outputs
I 7.0 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Power down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I ±12 mA output drive (VCC = 3.0V)
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX162374GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCX162374MEA
(Note 3)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500442
www.fairchildsemi.com
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEn
CPn
I0–I15
O0–O15
NC
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G O12 O11
H O14 O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE2
4
CP1
NC
VCC
GND
GND
GND
VCC
NC
CP2
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
CP1
OE1
L
L
LL
XH
I0–I7
H
L
X
X
Outputs
O0–O7
H
L
O0
Z
Inputs
CP2
OE2
L
L
I8–I15
H
L
LL
X
XH
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of CP
Outputs
O8–O15
H
L
O0
Z
www.fairchildsemi.com
2
|