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74HCT175D 반도체 회로 부품 판매점

Quad D-type flip-flop with reset; positive-edge trigger



Philips 로고
Philips
74HCT175D 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT175
Quad D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08


74HCT175D 데이터시트, 핀배열, 회로
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger 74HC/HCT175
FEATURES
Four edge-triggered D flip-flops
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All Qn outputs will be forced LOW independently of clock
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL propagation delay
CL = 15 pF; VCC = 5 V
CP to Qn, Qn
MR to Qn
tPLH propagation delay
CP to Qn, Qn
MR to Qn
fmax maximum clock frequency
CI input capacitance
CPD power dissipation capacitance per flip-flop notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC HCT
UNIT
17 16 ns
15 19 ns
17 16 ns
15 16 ns
83 54 MHz
3.5 3.5 pF
32 34 pF
1998 Jul 08
2




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74HCT175D flip-flop

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