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PDF 74AC374 Data sheet ( Hoja de datos )
| Número de pieza | 74AC374 | |
| Descripción | Octal D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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November 1988
Revised November 1999
74AC374 • 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
Features
s ICC and IOZ reduced by 50%
s Buffered positive edge-triggered clock
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s See 273 for reset version
s See 377 for clock enable version
s See 373 for transparent latch version
s See 574 for broadside pinout version
s See 564 for broadside pinout version with inverted
outputs
s ACT374 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74AC374SJ
74AC374MTC
M20D
MTC20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
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20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE 3-STATE Output Enable Input
O0–O7
3-STATE Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009959
www.fairchildsemi.com
1 page  
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width,
HIGH or LOW
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
2.0 5.5
6.0
1.0 4.0
4.5
−1.0
1.0
1.0
0 1.5
1.5
4.0 5.5
6.0
2.5 4.0
4.5
Units
ns
ns
ns
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CP to On
tPHL Propagation Delay
CP to On
tPZH Output Enable Time
tPZL Output Enable Time
tPHZ Output Disable Time
tPLZ Output Disable Time
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
TA = +25°C
CL = 50 pF
Min Typ Max
100 160
2.0 8.5 10.0
2.0 8.0 9.5
2.0 8.0 9.5
1.5 8.0 9.0
1.5 8.5 11.5
1.5 7.0 8.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
90
2.0 11.5
1.5 11.0
1.5 10.5
1.5 10.5
1.0 12.5
1.0 10.0
Units
MHz
ns
ns
ns
ns
ns
ns
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width,
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
1.0 5.5
5.5
0 1.5
1.5
2.5 5.0
5.0
Units
ns
ns
ns
Symbol
CIN
Parameter
Input Capacitance
Typ Units
Conditions
4.5 pF VCC = OPEN
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74AC374.PDF ] | |
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