74AC273PC 반도체 회로 부품 판매점
Octal D-Type Flip-Flop
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 Fairchild Semiconductor |
November 1988
Revised August 2000
74AC273 • 74ACT273
Octal D-Type Flip-Flop
General Description
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Ideal buffer for microprocessor or memory
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous master reset
s See 377 for clock enable version
s See 373 for transparent latch version
s See 374 for 3-STATE version
s Outputs source/sink 24 mA
s 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC273SJ
74AC273MTC
M20D
MTC20
20-Lead Small Ouwwtlwin.DeaPtaSahcekeat4gUe.co(mSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS009954
www.fairchildsemi.com
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Logic Diagram
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load ‘1'
Load ‘0'
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Inputs
Outputs
MR CP Dn
LXX
H H
H L
Qn
L
H
L
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74AC273PC flip-flop
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