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PDF 74AC175SC Data sheet ( Hoja de datos )
| Número de pieza | 74AC175SC | |
| Descripción | Quad D-Type Flip-Flop | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised November 1999
74AC175 • 74ACT175
Quad D-Type Flip-Flop
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran-
sition. Both true and complemented outputs of each flip-
flop are provided. A Master Reset input resets all flip-flops,
independent of the Clock or D-type inputs, when LOW.
Features
s ICC reduced by 50%
s Edge-triggered D-type inputs
s Buffered positive edge-triggered clock
s Asynchronous common reset
s True and complement output
s Outputs source/sink 24 mA
s ACT175 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC175SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT175SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT175SJ
M16D
16-Lead Small Ouwwtlwin.DeaPtaSahcekeat4gUe.co(mSOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT175PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D3
CP
MR
Q0–Q3
Q0–Q3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009936
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width
HIGH or LOW
tW MR Pulse Width, LOW
tREC
Recovery Time
MR to CP
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACT
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
2.0 4.5
4.5
1.0 3.0
3.0
1.0 1.0
1.0
1.0 1.0
1.0
2.5 4.5
4.5
2.0 3.5
3.5
2.5 4.5
5.0
2.0
−2.0
−1.0
3.5
0
0
3.5
0
0
Units
ns
ns
ns
ns
ns
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn or Qn
tPHL Propagation Delay
CP to Qn or Qn
tPLH Propagation Delay
MR to Qn
tPHL Propagation Delay
MR to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
Min
175
2.0
2.0
2.0
2.0
AC Operating Requirements for ACT
TA = +25°C
CL = 50 pF
Typ
236
6.0
7.0
6.0
5.5
Max
10.0
11.0
9.5
9.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
145
1.5 11.0
1.5 12.0
1.5 10.5
1.5 10.5
Units
MHz
ns
ns
ns
ns
Symbol
Parameter
tS (H)
tS (L)
tH
tW
Setup Time
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
CP Pulse Width
HIGH or LOW
tW MR Pulse Width, LOW
trec Recovery Time, MR to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
3.0 2.0
2.0
3.0 2.5
2.5
0 1.0
1.0
4.0 3.0
4.0 3.0
00
3.5
4.0
0
Units
ns
ns
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5
45.0
pF VCC = OPEN
pF VCC = 5.0V
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74AC175SC.PDF ] | |
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