74ABT74 판매점 - Dual D-type flip-flop

Philips Semiconductors

Octal transceiver with parity generator/checker

(3-State)

Product specification

74ABT657

FEATURES

• Combinational functions in one package

• Low static and dynamic power dissipation with high speed and

high output drive

• Output capability: +64mA/–32mA

• Power-up 3-State

• Latch-up protection exceeds 500mA per Jedec Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

DESCRIPTION

The 74ABT657 high-performance BiCMOS device combines low

static and dynamic power dissipation with high speed and high

output drive.

The 74ABT657 is an octal transceiver featuring non-inverting buffers

with 3-State outputs and an 8-bit parity generator/checker, and is

intended for bus-oriented applications. The buffers have a

guaranteed current sinking capability of 64mA. The

Transmit/Receive (T/R) input determines the direction of the data

flow through the bidirectional transceivers. Transmit (active-High)

enables data from A ports to B ports; Receive (active-Low) enables

data from B ports to A ports.

The Output Enable (OE) input disables both the A and B ports by

placing them in a high impedance condition when the OE input is

High. The parity select (ODD/EVEN) input gives the user the option

of odd or even parity systems. The parity (PARITY) pin is an output

from the generator/checker when transmitting from the port A to B

(T/R = High) and an input when receiving from port B to A port (T/R

= Low). When transmitting (T/R = High) the parity select

(ODD/EVEN) input is set, then the A port data is polled to determine

the number of High bits. The parity (PARITY) output then goes to the

logic state determined by the parity select (ODD/EVEN) setting and

by the number of High bits on port A. For example, if the parity

select (ODD/EVEN) is set Low (even parity), and the number of

High bits on port A is odd, then the parity (PARITY) output will be

High, transmitting even parity. If the number of High bits on port A is

even, then the parity (PARITY) output will be Low, keeping even

parity. When in receive mode (T/R = Low) the B port is polled to

determine the number of High bits. If parity select (ODD/EVEN) is

Low (even parity) and the number of Highs on port B is:

(1) odd and the parity (PARITY) input is High, then ERROR will be

High, signifying no error.

(2) even and the parity (PARITY) input is High, then ERROR will be

asserted Low, indicating an error.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

CI/O

ICCZ

Propagation delay

An to Bn or Bn to An

Input capacitance

I/O capacitance

Total supply current

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF; VCC = 5V

VI = 0V or VCC

Outputs disabled;

VO = 0V or VCC

Outputs disabled; VCC =5.5V

TYPICAL

3.3

500

UNIT

ORDERING INFORMATION

PACKAGES

24-Pin Plastic DIP

24-Pin plastic SO

24-Pin Plastic SSOP Type II

24-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +85°C

OUTSIDE NORTH AMERICA

74ABT657 N

74ABT657 D

74ABT657 DB

74ABT657 PW

NORTH AMERICA

74ABT657 N

74ABT657 D

74ABT657 DB

74ABT657PW DH

DWG NUMBER

SOT222-1

SOT137-1

SOT340-1

SOT355-1

PIN CONFIGURATION

T/R 1

A0 2

A1 3

A2 4

A3 5

A4 6

VCC 7

A5 8

A6 9

A7 10

ODD/EVEN 11

ERROR 12

TOP VIEW

24 OE

23 B0

22 B1

21 B2

20 B3

19 GND

18 GND

17 B4

16 B5

15 B6

14 B7

13 PARITY

SA00181

PIN DESCRIPTION

SYMBOL PIN NUMBER

NAME AND FUNCTION

13 PARITY Parity output

11 ODD/EVEN Parity select input

12 ERROR Error output

1 T/R Transmit/receive input

2, 3, 4, 5,

6, 8, 9, 10

A0 - A7 A port 3-State outputs

23, 22, 21, 20,

17, 16, 15, 14

B0 - B7

B port 3-State outputs

24 OE Output enable input (active-Low)

18, 19

GND

Ground (0V)

7 VCC Positive supply voltage

1995 Dec 11

2 853–1615 16106

74ABT74 반도체 회로 부품 판매점

Dual D-type flip-flop

국내 전력반도체 판매점

일반적인 전자부품 판매점

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