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PDF 74ABT377 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT377 | |
| Descripción | Octal D-Type Flip-Flop with Clock Enable | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 1993
Revised November 1999
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s Clock enable for address and data synchronization
applications
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s See ABT273 for master reset version
s See ABT373 for transparent latch version
s See ABT374 for 3-STATE version
s Output sink capability of 64 mA, source capability
of 32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
s Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT377CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT377CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CE
CP
Q0–Q7
Truth Table
Descriptions
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Operating Mode
Inputs
Output
Load “1”
Load “0”
Hold
CP CE Dn
I h
I I
h X
Qn
H
L
No Change
(Do Nothing) X H X No Change
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Clock Transition
h = HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
I = LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
© 1999 Fairchild Semiconductor Corporation DS011550
www.fairchildsemi.com
1 page  
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. VM = 1.5V
Input Pulse Requirements
Amplitude Rep. Rate
3.0V
1 MHz
FIGURE 3. Test Input Signal Requirements
tW
500 ns
AC Waveforms
tr
2.5 ns
tf
2.5 ns
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ABT377.PDF ] | |
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