74ABT374CSC 반도체 회로 부품 판매점
Octal D-Type Flip-Flop with 3-STATE Outputs
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 Fairchild Semiconductor |
November 1992
Revised November 1999
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Out-
put Enable (OE) are common to all flip-flops.
Features
s Edge-triggered D-type inputs
s Buffered positive edge-triggered clock
s 3-STATE outputs for bus-oriented applications
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number
74ABT374CSC
74ABT374CSJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMTC
74ABT374CPC
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input (Active Rising Edge)
OE 3-STATE Output Enable Input (Active LOW)
O0–O7
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011510
www.fairchildsemi.com
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs are in a high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Function Table
Inputs Internal Outputs
Function
OE CP D
Q
O
H H L NC
Z Hold
HHH
H L
H H
L L
L H
NC
L
H
L
H
L H L NC
L H H NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Z Hold
Z Load
Z Load
L Data Available
H Data Available
NC No Change in Data
NC No Change in Data
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT374CSC flip-flop
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상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
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관련 데이터시트
74ABT374CSC
Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor
74ABT374CSJ
Octal D-Type Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor