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74ABT374APWDH 반도체 회로 부품 판매점

Octal D-type flip-flop; positive-edge trigger 3-State



NXP Semiconductors 로고
NXP Semiconductors
74ABT374APWDH 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT374A
FEATURES
8-bit positive edge triggered register
3-State output buffers
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
Live insertion/extraction permitted
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
3.8
4
7
110
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374A PW
NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17,
18
D0-D7 Data inputs
2, 5, 6, 9,
12, 15, 16,
19
Q0-Q7 Data outputs
11 CP Clock pulse input (active rising edge)
10 GND Ground (0V)
20 VCC Positive supply voltage
SA00110
1995 Sep 06
1 853-1448 15704


74ABT374APWDH 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT374A
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11 CP
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SA00111
FUNCTION TABLE
INPUTS
OE CP
Dn
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
OPERATING MODE
L
L
l
h
L
H
L
Latch and read register
H
LX
NC
NC Hold
H
X
H Dn
NC
Dn
Z
Disable outputs
Z
H=
h=
L=
l=
NC=
X=
Z=
=
=
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
not a Low-to-High clock transition
LOGIC DIAGRAM
D0 D1 D2 D3 D4
3 4 7 8 13
1 EN
11
C1
3 1D
4
7
8
13
14
17
18
D5
14
D6
17
2
5
6
9
12
15
16
19
SA00112
D7
18
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
11
CP
1
OE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SA00113
1995 Sep 06
2




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74ABT374APWDH

Octal D-type flip-flop; positive-edge trigger 3-State - NXP Semiconductors