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PDF 74ABT16821A Data sheet ( Hoja de datos )
| Número de pieza | 74ABT16821A | |
| Descripción | 20-bit bus-interface D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
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74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 03 — 16 March 2010
Product data sheet
1. General description
The 74ABT16821A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to
a 3-state output buffer. The two sections of each register are controlled independently by
the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features and benefits
20-bit positive-edge triggered register
Multiple VCC and GND pins minimize switching noise
Live insertion and extraction permitted
Output capability: +64 mA and −32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
1 page  
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
1OE, 2OE
1Q0 to 1Q9
GND
VCC
2Q0 to 2Q9
2CP, 1CP
2D0 to 2D9
1D0 to1D9
Pin Description
1, 28
output enable input (active LOW)
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
data output
4, 11, 18, 25, 32, 39, 46, 53
ground (0 V)
7, 22, 35, 50
supply voltage
15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output
29, 56
clock pulse input (active rising edge)
42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input
55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input
6. Functional description
Table 3.
Input
nOE
L
L
L
H
H
Function table[1]
nCP
↑
↑
H or L
L or H
↑
nDx
l
h
X
X
Dn
Output
nQ0 to nQ9
L
H
NC
Z
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
Internal register Operating mode
L load + read register
H load + read register
NC hold
NC disable output
Dn disable output
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 16
5 Page 
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
12. Package outline
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
y
Z
56
pin 1 index
1
e
c
29
EA
X
HE v M A
A2
A1
28
wM
bp
Q
(A3)
A
Lp
L
detail X
θ
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1) E (1)
e
HE
L
Lp
Q
v
w
y Z (1) θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22 18.55
0.13 18.30
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25 0.18
0.1
0.85
0.40
8o
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT371-1
IEC
REFERENCES
JEDEC
JEITA
MO-118
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 9. Package outline SOT371-1 (SSOP56)
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
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