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Fairchild Semiconductor |
April 1988
Revised July 1999
74F175
Quad D-Type Flip-Flop
General Description
The 74F175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, LOW.
Features
s Edge-triggered D-type inputs
s Buffered positive edge-triggered clock
s Asynchronous common reset
s True and complement output
Ordering Code:
Order Number Package Number
Package Description
74F175SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F175PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009490
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
D0–D3
CP
MR
Q0–Q3
Q0–Q3
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs
Complement Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the state of their individual D inputs on the LOW-
to-HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH indepen-
dent of Clock or Data inputs. The 74F175 is useful for gen-
eral logic applications where a common Master Reset and
Clock are acceptable.
Truth Table
Inputs
MR CP Dn
L X X
HH
H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn Qn
LH
HL
LH
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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