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74F114SC 반도체 회로 부품 판매점

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears



Fairchild Semiconductor 로고
Fairchild Semiconductor
74F114SC 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
General Description
The 74F114 contains two high-speed JK flip-flops with
common Clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of Clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F114SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F114PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009474
www.fairchildsemi.com


74F114SC 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
J1, J2, K1, K2
CP
Data Inputs
Clock Pulse Input (Active Falling Edge)
CD
SD1, SD2
Q1, Q2, Q1, Q2
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/8.0
1.0/10.0
1.0/5.0
50/33.3
Truth Table
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/4.8 mA
20 µA/6.0 mA
20 µA/3.0 mA
1 mA/20 mA
Inputs
Outputs
SD CD CP
J
K
Q
Q
LHXXXHL
HLXXXLH
L L XXXHH
H H
H H
h h Q0 Q0
l hLH
H H
h l HL
H H
l
l Q0 Q0
H (h) = HIGH Voltage Level
L (h) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(one half shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74F114SC flip-flop

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Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears - Fairchild Semiconductor