74F113SC 반도체 회로 부품 판매점
Dual JK Negative Edge-Triggered Flip-Flop
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 Fairchild Semiconductor |
April 1988
Revised July 1999
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to SD sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number Package Number
Package Description
74F113SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F113SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F113PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009473
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
J1, J2, K1, K2
CP1, CP2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
U.L.
HIGH/LOW
1.0/1.0
1.0/4.0
1.0/5.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
−1 mA/20 mA
Inputs
Outputs
SD CP J K Q
Q
L X XX H L
H h h Q0 Q0
H l h L H
H h l H L
H l l Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage level
] = HIGH-to-LOW Clock Transition
X = Immaterial
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F113SC flip-flop
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관련 데이터시트
74F113SC
Dual JK Negative Edge-Triggered Flip-Flop - Fairchild Semiconductor
74F113SJ
Dual JK Negative Edge-Triggered Flip-Flop - Fairchild Semiconductor