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74F109SC 반도체 회로 부품 판매점

Dual JK Positive Edge-Triggered Flip-Flop



Fairchild Semiconductor 로고
Fairchild Semiconductor
74F109SC 데이터시트, 핀배열, 회로
April 1988
Revised November 1999
74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes
both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F109SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow Body
74F109SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide
74F109PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009471
www.fairchildsemi.com


74F109SC 데이터시트, 핀배열, 회로
Truth Table
Inputs
Outputs
SD CD CP
J
K
Q
Q
LHXXXHL
HLXXXLH
L L XXXHH
H H
I I LH
H H
hI
Toggle
H H
I h QQ
H H
h hHL
HHL XXQ
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Q
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2 Data Inputs
CP1, CP2
Clock Pulse Inputs (Active Rising Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
SD1, SD2
Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2 Outputs
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/1.8 mA
20 µA/1.8 mA
1 mA/20 mA
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74F109SC flip-flop

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