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74F109 반도체 회로 부품 판매점

Positive J-K positive edge-triggered flip-flops



NXP Semiconductors 로고
NXP Semiconductors
74F109 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74F109
Positive J-K positive edge-triggered
flip-flops
Product specification
IC15 Data Handbook
1990 Oct 23
Philips
Semiconductors


74F109 데이터시트, 핀배열, 회로
Philips Semiconductors
Postive J-K positive edge-triggered flip-flops
Product specification
74F109
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK design allows operation as a
D flip-flop by tying J and K inputs together. Although the clock input
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
PIN CONFIGURATION
RD0 1
J0 2
K0 3
CP0 4
SD0 5
Q0 6
Q0 7
GND 8
16 VCC
15 RD1
14 J1
13 K1
12 CP1
11 SD1
10 Q1
9 Q1
SF00135
TYPE
74F109
TYPICAL fmax
125MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
12.3mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F109N
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
I74F109N
16-pin plastic SO
N74F109D
I74F109D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
J0, J1
J inputs
1.0/1.0
K0, K1
K inputs
1.0/1.0
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
SD0, SD1
Set inputs (active Low)
1.0/3.0
RD0, RD1
Reset inputs (active Low)
1.0/3.0
Q0, Q1, Q0, Q1
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
4
5
1
12
11
15
VCC = Pin 16
GND = Pin 8
2 14 3 13
CP0 J0 J1 K0 K1
SD0
RD0
CP1
SD1
RD1 Q0 Q0 Q1 Q1
6 7 10 9
SF00136
2 1J
4 C1
3 1K
1R
5S
14 2J
12 C2
13 2K
15 R
11 S
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
1.0mA/20mA
6
7
10
9
SF00137
October 23, 1990
2
853–0337 00783




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74F109 flip-flop

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