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74ALVC74BQ 반도체 회로 부품 판매점

Dual D-type flip-flop with set and reset; positive-edge trigger



NXP Semiconductors 로고
NXP Semiconductors
74ALVC74BQ 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74ALVC74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 2003 Jan 24
2003 May 26


74ALVC74BQ 데이터시트, 핀배열, 회로
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74ALVC74
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay nCP to nQ, nQ
tPHL/tPLH propagation delay nSD, nRD to nQ, nQ
fmax maximum clock frequency
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.7 ns
2.6 ns
2.8 ns
2.7 ns
3.5 ns
2.5 ns
3.1 ns
2.3 ns
425 MHz
3.5 pF
35 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2003 May 26
2




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74ALVC74BQ flip-flop

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74ALVC74BQ

Dual D-type flip-flop with set and reset; positive-edge trigger - NXP Semiconductors