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74ALVC374D 반도체 회로 부품 판매점

Octal D-type flip-flop positive edge-trigger



NXP Semiconductors 로고
NXP Semiconductors
74ALVC374D 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74ALVC374
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
File under Integrated Circuits, IC24
2002 Feb 26


74ALVC374D 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger;
3-state
Product specification
74ALVC374
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS LOW power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
2000 V Human Body Model (JESD22-A 114-A)
200 V Machine Model (JESD22-A 115-A).
DESCRIPTION
The 74ALVC374 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC374 is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) input
and an output enable (OE) input are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘574’, but the ‘574’
has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay CP to Qn
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
outputs enable
outputs disabled
TYPICAL UNIT
3.1 ns
2.3 ns
2.5 ns
2.5 ns
3.5 pF
21 pF
13 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2002 Feb 26
2




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74ALVC374D flip-flop

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