74ALVC16821MTD 반도체 회로 부품 판매점
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
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 Fairchild Semiconductor |
October 2001
Revised October 2001
74ALVC16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16821 contains twenty non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications.
The 74ALVC16821 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
4.0 ns max for 3.0V to 3.6V VCC
4.9 ns max for 2.3V to 2.7V VCC
8.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74ALVC16821MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
CLKn
D0–D19
O0–O19
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500685
www.fairchildsemi.com
Connection Diagram
Logic Diagrams
Truth Tables
Inputs
Outputs
CLK1
OE1
D0–D9
O0–O9
X H X Z
LL L
L H H
L or H
L
X O0
Inputs
Outputs
CLK2
OE2
D10–D19 O10–O19
XHX Z
L L L
L H H
L or H
L
X O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before LOW-to-HIGH transition of Clock
= LOW-to-HIGH transition
Functional Description
The 74ALVC16821 contains twenty D-type flip-flops with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
each other. Control pins can be shorted together to obtain
full 20-bit operation. The following description applies to
each byte. The twenty flip-flops will store the state of their
individual D-type inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CLK) transition.
The 3-STATE standard outputs are controlled by the Out-
put Enable (OEn) input. When OEn is HIGH, the standard
outputs are in the high impedance mode but this does not
interfere with entering new data into the flip-flops.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC16821MTD flip-flop
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74ALVC16821MTD
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs - Fairchild Semiconductor
