파트넘버.co.kr 74ALS373N 데이터시트 PDF


74ALS373N 반도체 회로 부품 판매점

Latch/flip-flop



NXP Semiconductors 로고
NXP Semiconductors
74ALS373N 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALS373/74ALS374
Latch/flip–flop
Product specification
IC05 Data Handbook
Philips
Semiconductors
1991 Feb 08


74ALS373N 데이터시트, 핀배열, 회로
Philips Semiconductors
Latch/flip-flop
Product specification
74ALS373/74ALS374
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
FEATURES
8-bit transparent latch – 74ALS373
8-bit positive edge triggered register – 74ALS374
3-State output buffers
Common 3-State output register
Independent register and 3-State buffer operation
TYPE
TYPICAL
PROPAGATION DELAY
74ALS373
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
14mA
TYPE
74ALS374
TYPICAL
fMAX
50MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
17mA
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1
20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1
20-pin plastic SSOP
Type II
74ALS373DB, 74ALS374DB
SOT339-1
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D7
Data inputs
1.0/1.0
E (74ALS373)
Enable input (active-High)
1.0/1.0
OE Output enable inputs (active-Low)
1.0/1.0
CP (74ALS374)
Clock pulse input (active rising edge)
1.0/1.0
Q0 – Q7
3-State outputs
130/240
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
2.6mA/24mA
1991 Feb 08
2 853–1243 01670




PDF 파일 내의 페이지 : 총 13 페이지

제조업체: NXP Semiconductors

( nxp )

74ALS373N flip-flop

데이터시트 다운로드
:

[ 74ALS373N.PDF ]

[ 74ALS373N 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


74ALS373

Latch/flip-flop - NXP Semiconductors



74ALS373D

Latch/flip-flop - NXP Semiconductors



74ALS373DB

Latch/flip-flop - NXP Semiconductors



74ALS373N

Latch/flip-flop - NXP Semiconductors