(PDF) 74ALS112A Datasheet - Dual J-K negative edge-triggered flip-flop

Número de pieza	74ALS112A
Descripción	Dual J-K negative edge-triggered flip-flop
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductors 1 page Philips Semiconductors Dual J-K negative edge-triggered flip-flop Product specification 74ALS112A AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn or RD to Qn or Qn AC SETUP REQUIREMENTS SYMBOL PARAMETER tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (L) tREC Setup time, High or Low Jn, Kn to CPn Hold time, High or Low Jn, Kn to CPn CPn Pulse width high or Low SDn or RDn Pulse width Low Recovery time, SDn or RDn to CPn TEST CONDITION Waveform 1 Waveform 1 Waveform 2, 3 LIMITS Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN MAX 35 2.0 10.0 4.0 10.5 1.5 8.0 3.5 9.5 UNIT MHz ns ns TEST CONDITION Waveform 1 Waveform 1 Waveform 1 Waveform 2, 3 Waveform 2, 3 LIMITS Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN MAX 8.0 8.0 0.0 0.0 11.0 8.0 6.0 8.0 UNIT ns ns ns ns ns 1996 Jun 27 5 5 Page

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PDF 74ALS112A Data sheet ( Hoja de datos )