(PDF) 74ALS109A Datasheet - Dual J-K positive edge-triggered flip-flop with set and reset

Número de pieza	74ALS109A
Descripción	Dual J-K positive edge-triggered flip-flop with set and reset
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors 1 page Philips Semiconductors Dual J-K positive edge triggered flip-flop with set and reset Product specification 74ALS109A AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. Jn, Kn VM VM VM VM tsu(L) th(L) tsu(H) th(H) 1/fmax CPn VM VM tw(L) VM tw(H) tPLH tPHL Qn VM VM tPHL tPLH Qn VM VM SC00043 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Width, and Maximum Clock Frequency Jn, Kn SDn VM tw(L) CPn VM tREC VM tPLH Qn VM tPHL Qn VM SC00044 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width and Recovery Time for Set to Clock Jn, Kn RDn VM tw(L) CPn VM tREC VM tPLH Qn VM tPHL Qn VM SC00045 Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width and Recovery Time for Reset to Clock 1991 Feb 08 5 5 Page

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PDF 74ALS109A Data sheet ( Hoja de datos )