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74AHCT574D 반도체 회로 부품 판매점

Octal D-type flip-flop; positive edge-trigger; 3-state



NXP Semiconductors 로고
NXP Semiconductors
74AHCT574D 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74AHC574; 74AHCT574
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
File under Integrated Circuits, IC06
1999 Jun 16


74AHCT574D 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification
74AHC574;
74AHCT574
FEATURES
3-state non-inverting outputs for
bus oriented applications
8-bit positive, edge-triggered
register
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Independent register and 3-state
buffer operation
Common 3-state output enable
input
Output capability; bus driver
ICC category: MSI
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.
The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs.
The ‘574’ is functionally identical to the ‘374’, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CO
CPD
propagation delay
CP to Qn
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
CL = 15 pF; VCC = 5 V
CL = 15 pF; VCC = 5 V
VI = VCC or GND
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
TYPICAL
AHC
4.4
AHCT
4.4
UNIT
ns
130 130 MHz
4.0 4.0 pF
4.0 4.0 pF
10 12 pF
1999 Jun 16
2




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74AHCT574D flip-flop

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