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Fairchild Semiconductor |
September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild’s FACT Quiet Series technology
s Broadside pinout allows for easy board layout
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
CLRn
ENn
CPn
I0–I17
O0–O17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010953
www.fairchildsemi.com
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-trig-
gered flip-flops. These have 3-STATE outputs for bus sys-
tems organized with inputs and outputs on opposite sides.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. The
following description applies to each byte. The buffered
clock (CPn) and buffered Output Enable (OEn) are com-
mon to all flip-flops within that byte. The flip-flops will store
the state of their individual D inputs that meet set-up and
hold time requirements on the LOW-to-HIGH CPn transi-
tion. With OEn LOW, the contents of the flip-flops are avail-
able at the outputs. When OEn is HIGH, the outputs go to
the impedance state. Operation of the OEn input does not
affect the state of the flip-flops. In addition to the Clock and
Output Enable pins, there are Clear (CLRn) and Clock
Enable (ENn) pins. These devices are ideal for parity bus
interfacing in high performance systems.
When CLRn is LOW and OEn is LOW, the outputs are
LOW. When CLRn is HIGH, data can be entered into the
flip-flops. When ENn is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the ENn is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table (Note 1)
Inputs
Internal
Output
OE CLR EN
HX L
HX L
CP
In
L
H
Q
L
H
On
Z
Z
HLXXX
L
Z
L LXXX
L
L
HHHXX
NC
Z
L HHX X
H H L
L
H H L
H
L H L
L
L H L
H
NC
L
H
L
H
NC
Z
Z
L
H
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC= No Change
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
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