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Fairchild Semiconductor |
November 1988
Revised November 1999
74AC374 • 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
Features
s ICC and IOZ reduced by 50%
s Buffered positive edge-triggered clock
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s See 273 for reset version
s See 377 for clock enable version
s See 373 for transparent latch version
s See 574 for broadside pinout version
s See 564 for broadside pinout version with inverted
outputs
s ACT374 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74AC374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE 3-STATE Output Enable Input
O0–O7
3-STATE Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009959
www.fairchildsemi.com
Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Truth Table
Inputs
Dn CP
H
L
XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
OE
L
L
H
Outputs
On
H
L
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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