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PDF 74ACT18823MTD Data sheet ( Hoja de datos )
| Número de pieza | 74ACT18823MTD | |
| Descripción | 18-Bit D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Features
s Broadside pinout allows for easy board layout
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
CLRn
ENn
CPn
I0–I17
O0–O17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS500294
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ACT18823MTD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74ACT18823MTD | 18-Bit D-Type Flip-Flop with 3-STATE Outputs | Fairchild Semiconductor |
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