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54175 반도체 회로 부품 판매점

Hex/Quad D Flip-Flops with Clear



National Semiconductor 로고
National Semiconductor
54175 데이터시트, 핀배열, 회로
June 1989
54174 DM54174 DM74174 54175 DM54175 DM74175
Hex Quad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) version features complementary
outputs from each flip-flop
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse When the clock input
is at either the high or low level the D input signal has no
effect at the output
Features
Y 174 contains six flip-flops with single-rail outputs
Y 175 contains four flip-flops with double-rail outputs
Y Buffered clock and direct clear inputs
Y Individual data input to each flip-flop
Y Applications include
Buffer storage registers
Shift registers
Pattern generators
Y Typical clock frequency 40 MHz
Y Typical power dissipation per flip-flop 38 mW
Y Alternate Military Aerospace device (54174 54175) is
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL F 6557 – 1
Order Number 54174DMQB 54174FMQB DM54174J
DM54174W or DM74174N
See NS Package Number J16A N16E or W16A
TL F 6557 – 2
Order Number 54175DMQB 54175FMQB DM54175J
DM54175W or DM74175N
See NS Package Number J16A N16E or W16A
Function Table (Each Flip-Flop)
C1995 National Semiconductor Corporation
Inputs
Outputs
Clear
Clock
D
Q
Q
L X XL H
H
u HH
L
H
u LL
H
H
L
X Q0
Q0
H e High Level (steady state)
L e Low Level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were established
e 175 only
TL F 6557
RRD-B30M105 Printed in U S A


54175 데이터시트, 핀배열, 회로
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54 and 54
b55 C to a125 C
DM74
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
tW
tSU
tH
tREL
TA
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 4)
Pulse Width
(Note 4)
Clock Low
Clock High
Clear
Data Setup Time (Note 4)
Data Hold Time (Note 4)
Clear Release Time (Note 4)
Free Air Operating Temperature
Min
45
2
0
25
10
20
20
0
30
b55
DM54174
Nom
5
Max
55
08
b0 8
16
30
125
DM74174
Min Nom Max
4 75 5
5 25
2
08
b0 8
16
0 30
25
10
20
20
0
30
0 70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
ns
C
’174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current Max
Input Voltage
VCC e Min II e b12 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
b1 5
04
1
V
V
V
mA
IIH
High Level Input Current
VCC e Max VI e 2 4V
IIL
Low Level Input Current
VCC e Max VI e 0 4V
IOS Short Circuit
Output Current
VCC e Max
(Note 2)
DM54
DM74
b20
b18
40
b1 6
b57
b57
mA
mA
mA
ICC Supply Current
VCC e Max (Note 3)
45 65 mA
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time
Note 3 With all outputs open and all DATA and CLEAR inputs at 4 5V ICC is measured after a momentary ground then 4 5V applied to the CLOCK input
Note 4 TA e 25 C and VCC e 5V
2




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