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DM74LS109A 반도체 회로 부품 판매점

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
DM74LS109A 데이터시트, 핀배열, 회로
June 1986
Revised March 2000
DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flop with
Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge
of the clock. The data on the J and K inputs may be
changed while the clock is HIGH or LOW as long as setup
and hold times are not violated. A low logic level on the
preset or clear inputs will set or reset the outputs regard-
less of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS109AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS109AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L H X XX
H
L
H L X XX
L
H
L L X X X H (Note 1) H (Note 1)
HH
LL
L
H
HH
HL
Toggle
HH
HH
LH
HH
Q0
H
Q0
L
HH
L XX
Q0
Q0
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↑ = Rising Edge of Pulse
Q0 = The output logic level of Q before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and/or clear inputs return to their inactive (HIGH) state.
© 2000 Fairchild Semiconductor Corporation DS006368
www.fairchildsemi.com


DM74LS109A 데이터시트, 핀배열, 회로
Absolute Maximum Ratings(Note 2)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
VCC Supply Voltage
4.75
VIH HIGH Level Input Voltage
2
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 3)
0
fCLK Clock Frequency (Note 4)
0
tW Pulse Width
Clock HIGH
18
(Note 3)
Preset LOW
15
Clear LOW
15
tW Pulse Width
(Note 4)
Clock HIGH
Preset LOW
25
20
Clear LOW
20
tSU Setup Time
Data HIGH
30
(Note 3)(Note 5)
Data LOW
20
tSU Setup Time
Data HIGH
35
(Note 5)(Note 4)
Data LOW
25
tH Hold Time (Note 6)
0
TA Free Air Operating Temperature
0
Note 3: CL = 15 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 4: CL = 50 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 5: The symbol () indicates the rising edge of the clock pulse is used for reference.
Note 6: TA = 25°C and VCC = 5V.
Nom
5
Max
5.25
0.8
0.4
8
25
20
70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
°C
www.fairchildsemi.com
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DM74LS109A flip-flop

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